| Type of Document |
Dissertation |
| Author |
DeBenedictis, Erik P.
|
| URN |
etd-09062006-111645 |
| Persistent URL |
http://resolver.caltech.edu/CaltechETD:etd-09062006-111645 |
| Title |
Techniques for testing integrated circuits |
| Degree |
PhD |
| Option |
Computer Science |
| Advisory Committee |
| Advisor Name |
Title |
| Carver Mead |
Committee Chair |
| Chuck Seitz |
Committee Member |
|
| Keywords |
|
| Date of Defense |
1982-05-05 |
| Availability |
unrestricted |
Abstract
A language is presented for describing tests of integrated circuits. The language has a high abstractive capability that enables test specifications to follow the structural or logical organization of a design. The test language is applied to a number of current design styles in a series of examples. Methods for designing integrated circuits for testability are demonstrated. An implementation of the test language through a test language interpreter and a tester is discussed. Tester designs are presented that will execute the test language with unusually high efficiency.
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| Files |
| Filename |
Size |
Approximate Download Time
(Hours:Minutes:Seconds)
|
| 28.8 Modem |
56K Modem |
ISDN (64 Kb) |
ISDN (128 Kb) |
Higher-speed Access |
| |
DeBenedictis_ep_1983.pdf |
8.31 Mb |
00:38:29 |
00:19:47 |
00:17:19 |
00:08:39 |
00:00:44 |
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