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Type of Document	Dissertation
Author	Manohar, Rajit
URN	etd-08112005-114144
Persistent URL	http://resolver.caltech.edu/CaltechETD:etd-08112005-114144
Title	The impact of asynchrony on computer architecture
Degree	PhD
Option	Computer Science
Advisory Committee	Advisor Name Title Alain J. Martin Committee Chair Alan H. Barr Committee Member K. Mani Chandy Committee Member Yaser S. Abu-Mostafa Committee Member
Keywords	none
Date of Defense	1998-06-25
Availability	restricted
Abstract The performance characteristics of asynchronous circuits are quite different from those of their synchronous counterparts. As a result, the best asynchronous design of a particular system does not necessarily correspond to the best synchronous design, even at the algorithmic level. The goal of this thesis is to examine certain aspects of computer architecture and design in the context of an asynchronous VLSI implementation. We present necessary and sufficient conditions under which the degree of pipelining of a component can be modified without affecting the correctness of an asynchronous computation. As an instance of the improvements possible using an asynchronous architecture, we present circuits to solve the prefix problem with average-case behavior better than that possible by any synchronous solution in the case when the prefix operator has a right zero. We show that our circuit implementations are area-optimal given their performance characteristics, and have the best possible average-case latency. At the level of processor design, we present a mechanism for the implementation of precise exceptions in asynchronous processors. The novel feature of this mechanism is that it permits the presence of a data-dependent number of instructions in the execution pipeline of the processor. Finally, at the level of processor architecture, we present the architecture of a processor with an independent instruction stream for branches. The instruction set permits loops and function calls to be executed with minimal control-flow overhead.
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