| Type of Document |
Master's Thesis |
| Author |
Kapre, Nachiket Ganesh
|
| Author's Email Address |
nachiket AT caltech.edu |
| URN |
etd-05312006-164059 |
| Persistent URL |
http://resolver.caltech.edu/CaltechETD:etd-05312006-164059 |
| Title |
Packet-switched on-chip FPGA overlay networks |
| Degree |
Master of Science |
| Option |
Computer Science |
| Advisory Committee |
| Advisor Name |
Title |
| Andre DeHon |
Committee Member |
|
| Keywords |
- packet switching
- network on chip
- butterfly fat tree
- on-chip
- NoC
- virtual channels
- adaptive routing
- BFT
- networks
- fpga
- packet switched
- cut-through
|
| Date of Defense |
2006-05-31 |
| Availability |
unrestricted |
Abstract
As we scale to larger chip capacities, it becomes possible to map large, concurrent applications to programmable fabrics. These applications often have irregular and dynamic communication requirements. Packet-switched networks provide efficient implementations for such applications on these fabrics. In this research, we show how to engineer high-performance packet-switched on-chip networks and provide quantitative comparisons between different kinds of these networks. We analyse different network topologies and justify selection of topologies based on experimental results. We investigate packet-switched and time-multiplexed styles of routing and provide guidance on which style is appropriate for which application.
|
| Files |
| Filename |
Size |
Approximate Download Time
(Hours:Minutes:Seconds)
|
| 28.8 Modem |
56K Modem |
ISDN (64 Kb) |
ISDN (128 Kb) |
Higher-speed Access |
| |
draft.pdf |
1.08 Mb |
00:04:58 |
00:02:33 |
00:02:14 |
00:01:07 |
00:00:05 |
|
